----------------------------------------------------------------------------------
-- Company:        RIT
-- Engineer:       Sam Skalicky
-- 
-- Create Date:    17:49:05 12/11/2009 
-- Design Name:    MSD P10662
-- Module Name:    Device - Behavioral 
-- Project Name:   Inout
-- Target Devices: Spartan 6 LXT
-- Tool versions:  QuestaSim-64 6.4c
-- Description:    This a bi-directional I2C/Two-wire port implementation in VHDL
--
-- Notes: Data is the bi-directional port, Clk is typeset as an inout in the idea that
-- the clock could be generated to this port (Master device) or recieved from this port
-- in the case of a Slave device. However it is not meant to be a bi-directional port
--
-- Dependencies:   None
--
-- Revision: 1.0
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity I2Cslave is
    port( --inputs from bus
          I2CData : inout std_logic;
          I2CClk : in std_logic;
          --inputs from device (setup)
          I2CAddress : in std_logic_vector(6 downto 0);
          SendData : in std_logic_vector(7 downto 0);
          FPGA_CLK : in std_logic;
          --outputs to device
          Operation : out std_logic;
          RegID : out std_logic_vector(7 downto 0);
          RecData : out std_logic_vector(7 downto 0);
          Operation_Valid : std_logic:='0';
          RegID_Valid : out std_logic:='0';
          RecData_Valid : out std_logic:='0'
        );
end I2Cslave;
